The invention generally relates to semiconductor manufacturing and integrated circuits and, more particularly, to electrostatic discharge protection circuits and methods of protecting an integrated circuit from an electrostatic discharge event.
Electrostatic discharge (ESD) protection circuits are elements of an integrated circuit network and are used to protect the constituent semiconductor devices and circuits of the integrated circuit network against ESD induced damage. An integrated circuit may be exposed to transient electrostatic discharge (ESD) events that can direct potentially large and damaging ESD currents to the integrated circuits of the chip. An ESD event involves an electrical discharge from a source, such as the human body or a metallic object, over a short duration and can deliver a large amount of current to the integrated circuit. An integrated circuit may be protected from ESD events by, for example, incorporating an ESD protection circuit into the chip. The ESD protection circuit is usually connected to vulnerable terminals and, when activated, diverts ESD stress so that the integrated circuit network is bypassed and protected. During normal operation of the integrated circuit network, the ESD protection circuit is maintained in a deactivated condition.
Improved electrostatic discharge protection circuits are needed that provide electrostatic discharge protection and improved methods are needed for protecting an integrated circuit from an electrostatic discharge event.